Increasing the Effective Memory Bandwidth in Multivector Processors

In the memory system of multivector processors, the interferences between concurrent vector streams cause the loss of cycles that makes the effective throughput be lower than the required throughput. Then, the work of the functional units is delayed. Using the classical order to access the vector stream elements, the vector stream references the memory modules using a temporal distribution that depends on the element specification pattern; in general, different specification patterns determine different temporal distributions of memory modules. Concurrent vector streams using different temporal distributions to access the memory modules could imply the presence of memory module conflicts even if the request rate of all the concurrent streams to every memory module is less than or equal to it service rate. This paper proposes an access order to reference the vector stream elements. This new order is imposed by a temporal distribution of memory modules that reduces the average memory access time in vector processors. This temporal distribution only depends on the memory system configuration and on the memory modules referenced by the vector stream. When the request rate of all the vector streams to every memory module is less than or equal to its service rate, the proposed order obtains the required bandwidth. Under other conditions, the proposed order reduces the number of lost cycles, and the effective throughput increases.